Method for forming a low leakage contact in a CMOS imager

ABSTRACT

An imaging device formed as a CMOS semiconductor integrated circuit includes a doped polysilicon contact line between the floating diffusion region and the gate of a source follower output transistor. The doped polysilicon contact line in the CMOS imager decreases leakage from the diffusion region into the substrate which may occur with other techniques for interconnecting the diffusion region with the source follower transistor gate. Additionally, the CMOS imager having a doped polysilicon contact between the floating diffusion region and the source follower transistor gate allows the source follower transistor to be placed closer to the floating diffusion region, thereby allowing a greater photo detection region in the same sized imager circuit.

FIELD OF THE INVENTION

[0001] The invention relates generally to improved semiconductor imagingdevices and in particular to a silicon imaging device which can befabricated using a standard CMOS process. Particularly, the inventionrelates to CMOS imager having a doped polysilicon contact from adiffusion node to a gate of a source follower transistor.

DISCUSSION OF RELATED ART

[0002] There are a number of different types of semiconductor-basedimagers, including charge coupled devices (CCDs), photodiode arrays,charge injection devices and hybrid focal plane arrays. CCDs are oftenemployed for image acquisition and enjoy a number of advantages whichmakes it the incumbent technology, particularly for small size imagingapplications. CCDs are also capable of large formats with small pixelsize and they employ low noise charge domain processing techniques.However, CCD imagers also suffer from a number of disadvantages. Forexample, they are susceptible to radiation damage, they exhibitdestructive read out over time, they require good light shielding toavoid image smear and they have a high power dissipation for largearrays. Additionally, while offering high performance, CCD arrays aredifficult to integrate with CMOS processing in part due to a differentprocessing technology and to their high capacitances, complicating theintegration of on-chip drive and signal processing electronics with theCCD array. While there has been some attempts to integrate on-chipsignal processing with the CCD array, these attempts have not beenentirely successful. CCDs also must transfer an image by line chargetransfers from pixel to pixel, requiring that the entire array be readout into a memory before individual pixels or groups of pixels can beaccessed and processed. This takes time. CCDs may also suffer fromincomplete charge transfer from pixel to pixel during charge transferwhich also results in image smear.

[0003] Because of the inherent limitations in CCD technology, there isan interest in CMOS imagers for possible use as low cost imagingdevices. A fully compatible CMOS sensor technology enabling a higherlevel of integration of an image array with associated processingcircuits would be beneficial to many digital applications such as, forexample, in cameras, scanners, machine vision systems, vehiclenavigation systems, video telephones, computer input devices,surveillance systems, auto focus systems, star trackers, motiondetection systems, image stabilization systems and data compressionsystems for high-definition television.

[0004] The advantages of CMOS imagers over CCD imagers are that CMOSimagers have a low voltage operation and low power consumption; CMOSimagers are compatible with integrated on-chip electronics (controllogic and timing, image processing, and signal conditioning such as A/Dconversion); CMOS imagers allow random access to the image data; andCMOS imagers have lower fabrication costs as compared with theconventional CCD since standard CMOS processing techniques can be used.Additionally, low power consumption is achieved for CMOS imagers becauseonly one row of pixels at a time needs to be active during the readoutand there is no charge transfer (and associated switching) from pixel topixel during image acquisition. On-chip integration of electronics isparticularly advantageous because of the potential to perform manysignal conditioning functions in the digital domain (versus analogsignal processing) as well as to achieve a reduction in system size andcost.

[0005] A CMOS imager circuit includes a focal plane array of pixelcells, each one of the cells including either a photogate, a photodiode,or a photoconductor overlying a substrate for accumulatingphoto-generated charge in the underlying portion of the substrate. Areadout circuit is connected to each pixel cell and includes at least anoutput field effect transistor formed in the substrate and a chargetransfer section formed on the substrate adjacent the photogate,photodiode, or photoconductor having a sensing node, typically afloating diffusion node, connected to the gate of an output transistor.The imager may include at least one electronic device such as atransistor for transferring charge from the underlying portion of thesubstrate to the floating diffusion node and one device, also typicallya transistor, for resetting the node to a predetermined charge levelprior to charge transference.

[0006] In a CMOS imager, the active elements of a pixel cell perform thenecessary functions of: (1) photon to charge conversion; (2)accumulation of image charge; (3) transfer of charge to the floatingdiffusion node accompanied by charge amplification; (4) resetting thefloating diffusion node to a known state before the transfer of chargeto it; (5) selection of a pixel for readout; and (6) output andamplification of a signal representing pixel charge. Photo charge may beamplified when it moves from the initial charge accumulation region tothe floating diffusion node. The charge at the floating diffusion nodeis typically converted to a pixel output voltage by a source followeroutput transistor. The photosensitive element of a CMOS imager pixel istypically either a depleted p-n junction photodiode or a field induceddepletion region beneath a photogate or a photoconductor. Forphotodiodes, image lag can be eliminated by completely depleting thephotodiode upon readout.

[0007] CMOS imagers of the type discussed above are generally known asdiscussed, for example, in Nixon et al., “256×256 CMOS Active PixelSensor Camera-on-a-Chip,” IEEE Journal of Solid-State Circuits, Vol.31(12) pp. 2046-2050, 1996; Mendis et al, “CMOS Active Pixel ImageSensors,” IEEE Transactions on Electron Devices, Vol. 41(3) pp. 452-453,1994 as well as U.S. Pat. No. 5,708,263 and U.S. Pat. No. 5,471,515,which are herein incorporated by reference.

[0008] To provide context for the invention, an exemplary CMOS imagingcircuit is described below with reference to FIG. 1. The circuitdescribed below, for example, includes a photogate for accumulatingphoto-generated charge in an underlying portion of the substrate. Itshould be understood that the CMOS imager may include a photodiode orother image to charge converting device, in lieu of a photogate, as theinitial accumulator for photo-generated charge.

[0009] Reference is now made to FIG. 1 which shows a simplified circuitfor a pixel of an exemplary CMOS imager using a photogate and having apixel photodetector circuit 14 and a readout circuit 60. It should beunderstood that while FIG. 1 shows the circuitry for operation of asingle pixel, that in practical use there will be an M×N array of pixelsarranged in rows and columns with the pixels of the array accessed usingrow and column select circuitry, as described in more detail below.

[0010] The photodetector circuit 14 is shown in part as across-sectional view of a semiconductor substrate 16 typically a p-typesilicon, having a surface well of p-type material 20. An optional layer18 of p-type material may be used if desired, but is not required.Substrate 16 may be formed of, for example, Si, SiGe, Ge, and GaAs.Typically the entire substrate 16 is p-type doped silicon substrate andmay contain a surface p-well 20 (with layer 18 omitted), but many otheroptions are possible, such as, for example p on p-substrates, p on p+substrates, p-wells in n-type substrates or the like. The terms wafer orsubstrate used in the description includes any semiconductor-basedstructure having an exposed surface in which to form the circuitstructure used in the invention. Wafer and substrate are to beunderstood as including, silicon-on-insulator (SOI) technology,silicon-on-sapphire (SOS) technology, doped and undoped semiconductors,epitaxial layers of silicon supported by a base semiconductorfoundation, and other semiconductor structures. Furthermore, whenreference is made to a wafer or substrate in the following description,previous process steps may have been utilized to form regions/junctionsin the base semiconductor structure or foundation.

[0011] An insulating layer 22 such as, for example, silicon dioxide isformed on the upper surface of p-well 20. The p-type layer may be ap-well formed in substrate 16. A photogate 24 thin enough to passradiant energy or of a material which passes radiant energy is formed onthe insulating layer 22. The photogate 24 receives an applied controlsignal PG which causes the initial accumulation of pixel charges in n+region 26. The n+ type region 26, adjacent one side of photogate 24, isformed in the upper surface of p-well 20. A transfer gate 28 is formedon insulating layer 22 between n+ type region 26 and a second n+ typeregion 30 formed in p-well 20. The n+ regions 26 and 30 and transfergate 28 form a charge transfer transistor 29 which is controlled by atransfer signal TX. The n+ region 30 is typically called a floatingdiffusion region. It is also a node for passing charge accumulatedthereat to the gate of a source follower transistor 36 described below.A reset gate 32 is also formed on insulating layer 22 adjacent andbetween n+ type region 30 and another n+ region 34 which is also formedin p-well 20. The reset gate 32 and n+ regions 30 and 34 form a resettransistor 31 which is controlled by a reset signal RST. The n+ typeregion 34 is coupled to voltage source VDD. The transfer and resettransistors 29, 31 are n-channel transistors as described in thisimplementation of a CMOS imager circuit in a p-well. It should beunderstood that it is possible to implement a CMOS imager in an n-wellin which case each of the transistors would be p-channel transistors. Itshould also be noted that while FIG. 1 shows the use of a transfer gate28 and associated transistor 29, this structure provides advantages, butis not required.

[0012] Photodetector circuit 14 also includes two additional n-channeltransistors, source follower transistor 36 and row select transistor 38.Transistors 36, 38 are coupled in series, source to drain, with thesource of transistor 36 also coupled over lead 40 to voltage source VDDand the drain of transistor 38 coupled to a lead 42. The drain of rowselect transistor 38 is connected via conductor 42 to the drains ofsimilar row select transistors for other pixels in a given pixel row. Aload transistor 39 is also coupled between the drain of transistor 38and a voltage source VSS. Transistor 39 is kept on by a signal VLNapplied to its gate.

[0013] The imager includes a readout circuit 60 which includes a signalsample and hold (S/H) circuit including a S/H n-channel field effecttransistor 62 and a signal storage capacitor 64 connected to the sourcefollower transistor 36 through row transistor 38. The other side of thecapacitor 64 is connected to a source voltage VSS. The upper side of thecapacitor 64 is also connected to the gate of a p-channel outputtransistor 66. The drain of the output transistor 66 is connectedthrough a column select transistor 68 to a signal sample output nodeVOUTS and through a load transistor 70 to the voltage supply VDD. Asignal called “signal sample and hold” (SHS) briefly turns on the S/Htransistor 62 after the charge accumulated beneath the photogateelectrode 24 has been transferred to the floating diffusion node 30 andfrom there to the source follower transistor 36 and through row selecttransistor 38 to line 42, so that the capacitor 64 stores a voltagerepresenting the amount of charge previously accumulated beneath thephotogate electrode 24.

[0014] The readout circuit 60 also includes a reset sample and hold(S/H) circuit including a S/H transistor 72 and a signal storagecapacitor 74 connected through the S/H transistor 72 and through the rowselect transistor 38 to the source of the source follower transistor 36.The other side of the capacitor 74 is connected to the source voltageVSS. The upper side of the capacitor 74 is also connected to the gate ofa p-channel output transistor 76. The drain of the output transistor 76is connected through a p-channel column select transistor 78 to a resetsample output node VOUTR and through a load transistor 80 to the supplyvoltage VDD. A signal called “reset sample and hold” (SHR) briefly turnson the S/H transistor 72 immediately after the reset signal RST hascaused reset transistor 31 to turn on and reset the potential of thefloating diffusion node 30, so that the capacitor 74 stores the voltageto which the floating diffusion node 30 has been reset.

[0015] The readout circuit 60 provides correlated sampling of thepotential of the floating diffusion node 30, first of the reset chargeapplied to node 30 by reset transistor 31 and then of the stored chargefrom the photogate 24. The two samplings of the diffusion node 30charges produce respective output voltages VOUTR and VOUTS of thereadout circuit 60. These voltages are then subtracted (VOUTS−VOUTR) bysubtractor 82 to provide an output signal terminal 81 which is an imagesignal independent of pixel to pixel variations caused by fabricationvariations in the reset voltage transistor 31 which might cause pixel topixel variations in the output signal.

[0016]FIG. 2 illustrates a block diagram for a CMOS imager having apixel array 200 with each pixel cell being constructed in the mannershown by element 14 of FIG. 1. FIG. 4 shows a 2×2 portion of pixel array200. Pixel array 200 comprises a plurality of pixels arranged in apredetermined number of columns and rows. The pixels of each row inarray 200 are all turned on at the same time by a row select line, e.g.,line 86, and the pixels of each column are selectively output by acolumn select line, e.g., line 42. A plurality of rows and column linesare provided for the entire array 200. The row lines are selectivelyactivated by the row driver 210 in response to row address decoder 220and the column select lines are selectively activated by the columndriver 260 in response to column address decoder 270. Thus, a row andcolumn address is provided for each pixel. The CMOS imager is operatedby the control circuit 250 which controls address decoders 220, 270 forselecting the appropriate row and column lines for pixel readout, androw and column driver circuitry 210, 260 which apply driving voltage tothe drive transistors of the selected row and column lines.

[0017]FIG. 3 shows a simplified timing diagram for the signals used totransfer charge out of photodetector circuit 14 of the FIG. 1 CMOSimager. The photogate signal PG is nominally set to 5V and the resetsignal RST is nominally set at 2.5V. As can be seen from the figure, theprocess is begun at time to by briefly pulsing reset voltage RST to 5V.The RST voltage, which is applied to the gate 32 of reset transistor 31,causes transistor 31 to turn on and the floating diffusion node 30 tocharge to the VDD voltage present at n+ region 34 (less the voltage dropVth of transistor 31). This resets the floating diffusion node 30 to apredetermined voltage (VDD−Vth). The charge on floating diffusion node30 is applied to the gate of the source follower transistor 36 tocontrol the current passing through transistor 38, which has been turnedon by a row select (ROW) signal, and load transistor 39. This current istranslated into a voltage on line 42 which is next sampled by providinga SHR signal to the S/H transistor 72 which charges capacitor 74 withthe source follower transistor output voltage on line 42 representingthe reset charge present at floating diffusion node 30. The PG signal isnext pulsed to 0 volts, causing charge to be collected in n+ region 26.A transfer gate voltage TX, similar to the reset pulse RST, is thenapplied to transfer gate 28 of transistor 29 to cause the charge in n+region 26 to transfer to floating diffusion node 30. It should beunderstood that for the case of a photogate, the transfer gate voltageTX may be pulsed or held to a fixed DC potential. For the implementationof a photodiode with a transfer gate, the transfer gate voltage TX mustbe pulsed. The new output voltage on line 42 generated by sourcefollower transistor 36 current is then sampled onto capacitor 64 byenabling the sample and hold switch 62 by signal SHS. The column selectsignal is next applied to transistors 68 and 70 and the respectivecharges stored in capacitors 64 and 74 are subtracted in subtractor 82to provide a pixel output signal at terminal 81.

[0018] The operation of the charge collection of the CMOS imager isknown in the art and is described in several publications such as Mendiset al., “Progress in CMOS Active Pixel Image Sensors,” SPIE Vol. 2172,pp. 19-29 1994; Mendis et al., “CMOS Active Pixel Image Sensors forHighly Integrated Imaging Systems,” IEEE Journal of Solid StateCircuits, Vol. 32(2), 1997; and Eric R, Fossum, “CMOS Image Sensors:Electronic Camera on a Chip,” IEDM Vol. 95 pages 17-25 (1995) as well asother publications. These references are incorporated herein byreference.

[0019] Prior CMOS imagers suffer from several drawbacks regarding thecharge flow and contact between the floating diffusion area 30 and thesource follower transistor 36. For example, tungsten metal, which istypically used to contact the floating diffusion region and the sourcefollower transistor, is deposited with tungsten fluoride and a reactionsometimes takes place between the tungsten fluoride and the substrateresulting in the formation of silicon fluoride which creates worm holesin the substrate. These worm holes create a conductive channel forcurrent to leak into the substrate, creating a poor performance for theimager. Since the size of the pixel electrical signal is very small dueto the collection of photons in the photo array, the signal to noiseratio of the pixel should be as high as possible within a pixel. Thus,leakage into the substrate is a significant problem to be avoided inCMOS imagers.

[0020] Conventional floating diffusion regions also typically have ahighly n+ doped region to facilitate an ohmic metal-semiconductorcontact between the contact metallization and the underlying n-dopedsilicon region to achieve charge transfer to the source followertransistor 36. However, this same highly doped n+ region 30 createscurrent leakage into the substrate due to high electric fields caused bythe abrupt junction. Also, typically there must be an over etch of thecontact to account for non-uniformities across the wafer andnon-uniformity of an insulating layer thickness. Accordingly, resistancein the conductive path between the floating diffusion region and gate ofthe source follower transistor should be as low as possible withoutresulting in added junction leakage.

[0021] Several of the above-described drawbacks can be seen from FIGS.5-8 which show a side view of several CMOS imagers of the prior art. Itshould be understood that similar reference numbers correspond tosimilar elements for FIGS. 5-7. Reference is now made to FIG. 5. Thisfigure shows the region between the floating diffusion and the sourcefollower transistor of a prior CMOS imager having a photogate as thephotoactive area and which further includes a transfer gate. The imager100 is provided with three doped regions 143, 126 and 115, which aredoped to a conductivity type different from that of the substrate, forexemplary purposes regions 143, 126 and 115 are treated as n type, whichare within a p-well of a substrate. The first doped region 143 is thephotosite charge collector, and it underlies a portion of the photogate142, which is a thin layer of material transparent or partiallytransparent to radiant energy, such as polysilicon, indium-tin oxide ortin oxide. An insulating layer 140 of silicon dioxide, silicon nitride,or other suitable material is formed over a surface of the doped layer143 of the substrate between the photogate 142 and first doped region143.

[0022] The second doped region 126 transfers charge collected by thephotogate 142 and it serves as the source for the transfer transistor128. The transfer transistor 128 includes a transfer gate 139 formedover a gate oxide layer 140. The transfer gate 139 has insulatingspacers 149 formed on its sides.

[0023] The third doped region 115 is the floating diffusion region andis connected to a gate 136 of a source follower transistor by contactlines 125, 127, 129 which are typically metal contact lines as describedin more detail below. The imager 100 typically includes a highly n+doped region 120 within n-doped region 115 under the floating diffusionregion contact 125 which provides good ohmic contact of the contact 125with the n-doped region 115. The floating diffusion contact 125 connectsn+ region 120 of the floating diffusion region with the gate 136 of thesource follower transistor. In other embodiments of the prior art, theentire region 115 may be doped n+ thereby eliminating the need for n+region 120.

[0024] The source and drain regions of the source follower transistorare not seen in FIG. 5 as they are perpendicular to the page but are oneither side of gate 136. The source follower gate 136 is usually formedof a doped polysilicon which may be silicided and which is depositedover a gate oxide 140, such as silicon dioxide. The floating diffusioncontact 125 is usually formed of a tungsten plug typically a Ti/TiN/Wmetallization stack as described in further detail with respect to FIG.8. The floating diffusion contact 125 is formed in an insulating layer135 which is typically an undoped oxide followed by the deposition of adoped oxide such as a BPSG layer 135 deposited over the substrate. Thetungsten metal which forms the floating diffusion/source followercontact 125 is typically deposited by CVD using a tungsten fluoride suchas WF₆.

[0025] Typically, the layer 135 must be etched with a selective dry etchprocess prior to depositing the tungsten plug connector 125. The imager100 also includes a source follower contact 127 formed in layer 135 in asimilar fashion to floating diffusion contact 125. Source followercontact 127 is also usually formed of a tungsten plug typically aTi/TiN/W metallization stack as described in further detail below. Thefloating diffusion contact 125 and the source follower contact 127 areconnected by a metal layer 129 formed over layer 135. Typically metallayer 129 is formed of aluminum, copper, tungsten or any other metal.

[0026] Separating the source follower transistor gate 136 and thefloating diffusion region 115 is a field oxide layer 132, which servesto surround and isolate the cells. The field oxide 132 may be formed bythermal oxidation of the substrate using the Local Oxidation of Silicon(LOCOS) or by the Shallow Trench Isolation (STI) process which involvethe chemical vapor deposition of an oxide material.

[0027] It should be understood that while FIG. 5 shows an imager havinga photogate as the photoactive area and additionally includes a transfertransistor, additional CMOS imager structures are also well known. Forexample, CMOS imagers having a photodiode or a photoconductor as thephotoactive area are known. Additionally, while a transfer transistorhas some advantages as described above, it is not required. Accordingly,the FIG. 5 structure is not limiting of the environment of the inventionbut is only used to illustrate the problem to be solved by theinvention.

[0028] The prior art metal contacts 125, 127 described with reference toFIG. 5 typically include a thin layer 123 formed of titanium, titaniumnitride or a mixture thereof formed in the etched space in the layer135. A tungsten plug 122 is then filled in the etched space in the layer135 inside the thin layer 123. The contact 125 contacts n+ region 120and forms a TiSi₂ area 121 by a reaction between the titanium from layer123 with the silicon substrate in n+ region 120.

[0029] Reference is now made to FIG. 6. This figure illustrates anenlarged and partially cut away side view of a semiconductor imagerundergoing a processing method according to the prior art. The imager104 has the floating diffusion region 115 having an n+ doped region 120and the source follower transistor gate 136 already formed therein. Thefloating diffusion 115 and the source follower gate 136 are under layer135, which, as noted, is preferably composed of oxides, typically alayered structure of an undoped and doped, i.e., BPSG, oxides. A resist155 is applied to layer 135 in order to etch through layer 135 to formthe contacts to the floating diffusion region 115 and the sourcefollower transistor gate 136. Layer 135 is then etched to form the hole156 in layer 135 for the floating diffusion contact 125 and hole 157 inlayer 135 for the source follower transistor contact 127 as shown inFIG. 7. However, as can be seen from FIG. 7, since the field oxide 132and layer 135 are both similar oxides it is difficult to control theetching process when attempting to align the hole 156 with the edge ofthe field oxide 132. In fact, the etching process often etches deep intothe n+ region 120 or etches through the exposed edge of the field oxide132 causing charge leakage to the substrate as shown by the arrows inFIG. 7. Etching deep into the n+ region 120 results in poor contactresistance to the n+ region 120. Etching through the n+ region 120 orthrough the exposed region of the filed oxide 132 can result in chargeleakage to the substrate.

[0030] Reference is now made to FIG. 8. This figure illustrates thefloating diffusion contact 125 between the floating diffusion region 115and the metal layer 129 which are illustrated in FIGS. 5-7. It should beunderstood that while FIG. 8 shows a typical connection between thefloating diffusion 115 and the metal layer 129, the source followercontact 127 deposited in an etched hole in layer 135 is formed ofsimilar materials. The contact includes a thin layer 123 formed oftitanium, titanium nitride or a mixture thereof formed in the etchedspace in the layer 135. A tungsten plug 122 is then filled in the etchedspace in the layer 135 inside the thin layer 123. The contact 125contacts n+ region 120 and forms a TiSi₂ area 121 by a reaction betweenthe titanium from layer 123 with the silicon substrate in n+ region 120.

[0031] The devices described with reference to FIGS. 5-8 have severaldrawbacks. For example, during etching, caution must be taken to avoidetching through the n+ layer 120 or even deep into n-doped region 115where the n-type dopant concentration is reduced. Additionally, when thetungsten metal is deposited by CVD using tungsten fluoride, a reactionsometimes takes place between the tungsten fluoride and the substrateresulting in the formation of silicon fluoride which creates worm holesthrough the n+ region 120 and into the substrate. These worm holes maycreate a channel for current to leak into the substrate, creating a poorperformance for the imager. While Ti/TiN barrier layers are deposited toform a good ohmic contact to the n+ region due to the TiSi₂ reaction andprovide a TiN barrier between the W metallization and the Si substrate,worm holes and contact leakage still occur. Also, the prior art floatingdiffusion region 115 included the highly n+ region 120 to provide anohmic contact; however, this same highly doped n+ region sets up highelectric fields with respect to the p-type region under field oxideregion 132 which fosters current leakage into the substrate.Accordingly, a better low resistance conductive path is required betweenregion 120 and gate 136 of the source follower transistor which providesa good ohmic contact, while avoiding substrate leakage.

SUMMARY OF THE INVENTION

[0032] The present invention provides a CMOS imager in which thefloating diffusion is connected to a gate of the source followertransistor by a doped polysilicon contact. The doped polysilicon contactprovides a better ohmic contact with less leakage into the substrate.The present invention also provides doped polysilicon plugs to connectthe floating diffusion and the gate of the source follower transistor bya metal interconnector formed over a BPSG layer. The doped polysiliconcontact between the floating diffusion region and the gate of the sourcefollower transistor also allows the floating diffusion region and thesource follower transistor to be placed closer together, therebyreducing size of a pixel and allowing an increased photo area per cellsize which, it turn, increases the signal to noise ratio of the imager.In addition, the problems with worm holes and connecting of the floatingdiffusion contact are completely avoided as there is no need for thehighly doped n+ region 120 in the present invention and additionally noneed for any metallization to be directly in contact with the siliconsubstrate at the floating diffusion node.

[0033] The above and other advantages and features of the invention willbe more clearly understood from the following detailed description whichis provided in connection with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0034]FIG. 1 is a representative circuit of a CMOS imager.

[0035]FIG. 2 is a block diagram of a CMOS active pixel sensor chip.

[0036]FIG. 3 is a representative timing diagram for the CMOS imager.

[0037]FIG. 4 is a representative pixel layout showing a 2×2 pixel layoutaccording to one embodiment of the present invention.

[0038]FIG. 5 is a partially cut away side view of a semiconductor imagerhaving a photogate and a transfer gate according to the prior art.

[0039]FIG. 6 shows a partially cut away side view of a semiconductorimager undergoing a processing method according to the prior art.

[0040]FIG. 7 shows a partially cut away side view of a semiconductorimager undergoing a processing method according to the prior artsubsequent to FIG. 6.

[0041]FIG. 8 is an enlarged view of a floating diffusion contactaccording to the prior art.

[0042]FIG. 9 shows a partially cut away side view of a semiconductorimager of a first embodiment of the present invention at an intermediatestep of processing.

[0043]FIG. 10 shows a partially cut away side view of a semiconductorimager of the present invention subsequent to FIG. 9.

[0044]FIG. 11 shows a partially cut away side view of a semiconductorimager of the present invention subsequent to FIG. 10.

[0045]FIG. 12 shows a partially cut away side view of a semiconductorimager of the present invention subsequent to FIG. 11.

[0046]FIG. 13 shows a partially cut away side view of a semiconductorimager of the present invention subsequent to FIG. 12.

[0047]FIG. 14 shows a partially cut away side view of a semiconductorimager of the present invention subsequent to FIG. 13.

[0048]FIG. 15 shows a partially cut away side view of a semiconductorimager undergoing a processing method according to a second embodimentthe present invention.

[0049]FIG. 16 shows a partially cut away side view of a semiconductorimager undergoing a processing method according to a second embodimentthe present invention subsequent to FIG. 15.

[0050]FIG. 17 shows a partially cut away side view of a semiconductorimager undergoing a processing method according to a second embodimentthe present invention subsequent to FIG. 16.

[0051]FIG. 18 shows a partially cut away side view of a semiconductorimager undergoing a processing method according to a second embodimentthe present invention subsequent to FIG. 17.

[0052]FIG. 19 shows a partially cut away side view of a semiconductorimager undergoing a processing method according to a second embodimentthe present invention subsequent to FIG. 18.

[0053]FIG. 20 shows a partially cut away side view of a semiconductorimager undergoing a processing method according to a second embodimentthe present invention subsequent to FIG. 19.

[0054]FIG. 21 shows a partially cut away side view of a semiconductorimager undergoing a processing method according to a second embodimentthe present invention subsequent to FIG. 20.

[0055]FIG. 22 is an illustration of a computer system having a CMOSimager according to the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0056] In the following detailed description, reference is made to theaccompanying drawings which form a part hereof, and in which is shown byway of illustration specific embodiments in which the invention may bepracticed. These embodiments are described in sufficient detail toenable those skilled in the art to practice the invention, and it is tobe understood that other embodiments may be utilized, and thatstructural, logical and electrical changes may be made without departingfrom the spirit and scope of the present invention.

[0057] The terms “wafer” and “substrate” are to be understood asincluding silicon-on-insulator (SOI) or silicon-on-sapphire (SOS)technology, doped and undoped semiconductors, epitaxial layers ofsilicon supported by a base semiconductor foundation, and othersemiconductor structures. Furthermore, when reference is made to a“wafer” or “substrate” in the following description, previous processsteps may have been utilized to form regions or junctions in the basesemiconductor structure or foundation. In addition, the semiconductorneed not be silicon-based, but could be based on silicon-germanium,germanium, or gallium arsenide.

[0058] The term “pixel” refers to a picture element unit cell containinga photosensor and transistors for converting electromagnetic radiationto an electrical signal. For purposes of illustration, a representativepixel is illustrated in the figures and description herein, andtypically fabrication of all pixels in an imager will proceedsimultaneously in a similar fashion. The following detailed descriptionis, therefore, not to be taken in a limiting sense, and the scope of thepresent invention is defined by the appended claims.

[0059] The invention is now described with reference to FIGS. 9-22. FIG.9 shows a partially cut away cross-sectional view of a CMOSsemiconductor wafer similar to that shown in FIG. 1. It should beunderstood that similar reference numbers correspond to similar elementsfor FIGS. 9-21. FIG. 9 shows the region between the floating diffusionand the source follower transistor for an imager having a photodiode asthe photosensitive area and which does not include a transfer gate. Aswith FIG. 5 above, the source follower transistor source and drainregions are in a plane perpendicular to FIG. 9. The pixel cell 300includes a substrate which includes a p-type well 311 formed in asubstrate. The pixel cell 300 includes an n-doped region 315 which formsthe floating diffusion region. It should be understood that the CMOSimager of the present invention can also be fabricated using p-dopedregions in an n-well.

[0060] The pixel cell 300 also includes a field oxide regions 332, whichmay be formed by thermal oxidation of the substrate using the LOCOSprocess or by the STI process which involve the chemical vapordeposition of an oxide material. The field oxide regions 332 form anisolation around the source follower transistor area 330.

[0061] The pixel cell 300 includes an oxide or other insulating film 318deposited on the substrate by conventional methods. Preferably the oxidefilm 318 is formed of a silicon dioxide grown onto the substrate. Dopedregion 352 is formed in the substrate as shown in FIG. 9 in the areathat will later become the photodiode 350. It should be understood thatthe regions 315 and 352 may be doped to the same or different dopantconcentration levels. Additionally, while two separate doped regions areshown in the figure, a single doped region may incorporate both regions315 and 352. There may be other dopant implantations applied to thewafer at this stage of processing such as n-well and p-well implants ortransistor voltage adjusting implants. For simplicity, these otherimplants are not shown in the figure.

[0062] A doped polysilicon layer 320 is next deposited over the pixelcell 300 and patterned using resist and etching methods. The dopedpolysilicon layer 320 is deposited according to conventional methods.The doped polysilicon layer 320 will form the gate for the sourcefollower transistor. The gate also includes sidewall insulating spacers356, all as shown in FIG. 10.

[0063] An insulating layer 360 is deposited and planarized as shown inFIG. 11. The layer 360 may include materials such as BPSG, PSG, BSG orthe like. A resist layer 355 is applied to the pixel cell overinsulating layer 360 as shown in FIG. 12. A space in the resist layer355 is provided which is aligned over n-doped region 315 and a space inthe resist layer 355 is also provided over source follower transistorgate 320. The insulating layer 360 and insulating layer 318 over then-doped region 315 are then etched as shown in FIG. 13. The insulatinglayer over the source follower transistor gate 320 is also etched asshown.

[0064] A doped polysilicon layer 340 is then deposited in the holesetched in the insulating layer 360 to connect the n-doped region 315 andthe source follower transistor gate 320 as shown in FIG. 14. The dopedpolysilicon layer 340 may also be formed of a composite layeredstructure of doped polysilicon/refractory metal silicide or dopedpolysilicon/refractory metal silicide/insulator for improvedconductivity. Preferably the refractory metal silicide is a tungsten,cobalt, or titanium silicide. The layered structure could also be alayered structure of polysilcon/barrier metal/metal where the barriermetal is Ti/TiN, TaNx, TiN, MoNx, or WNx and where the metal is W, Ta orMo.

[0065] The n-type dopant from in the doped polysilicon layer 340diffuses out of the doped polysilicon and into n-doped region 315 toform contact region 325. Contact region 325 forms a good low leakagedamage free contact to n-doped region 315. It is also possible to add ann-type dopant implant into the silicon prior to polysilicon depositionto improve leakage and contact resistance.

[0066] After the processing to produce the imager shown in FIG. 14, thepixel cell 300 of the present invention is then processed according toknown methods to produce an operative imaging device. For example, apassivation layer may be applied and planarized and contact holes etchedtherein to form conductor paths to transistor gates, etc. Thepassivation layer may include materials such as BPSG, PSG, BSG or thelike. Conventional metal and insulation layers are formed over thepassivation layer and in the through holes to interconnect various partsof the circuitry in a manner similar to that used in the prior art (FIG.5) to form the floating diffusion region to source follower gateconnection. Additional insulating and passivation layers may also beapplied. The imager is fabricated to arrive at an operational apparatusthat functions generally similar to the imager depicted in FIGS. 1-4although it should be understood that FIG. 14 differs from the imagersshown in FIGS. 1-4 in that FIG. 14 includes a photodiode as thephotocollection device as opposed to the photogate 24 illustrated inFIG. 1. Additionally, FIG. 1 shows an optional transfer gate 28 which,as discussed above, is not needed, nor illustrated, with respect to theimager depicted in FIG. 14.

[0067] The doped polysilicon contact between the floating diffusionregion 315 and the source follower transistor gate 320 provides a goodcontact between the floating diffusion region 315 and the sourcefollower transistor gate 320 without using processing techniques whichmight cause charge leakage to the substrate during device operation. Thedoped polysilicon contact also allows the source follower transistor tobe placed closer to the floating diffusion region thereby allowing foran increased photosensitive area on the pixel and short conductorbetween the floating diffusion region and gate of the source followertransistor which increases the signal to noise ratio of the imager.

[0068] Reference is now made to FIGS. 15-21 which illustrate a partiallycut away side view of a semiconductor imager undergoing a processingmethod according to a second embodiment of the present invention. Itshould be understood that like reference numbers represent like elementsthrough the figures. Reference is first made to FIG. 15. The pixel cell301 includes a substrate which includes a p-type well 311 formed in asubstrate and an n-doped region 315 which forms the floating diffusionregion. It should be understood that the CMOS imager of the presentinvention can also be fabricated using p-doped regions in an n-well. Thepixel cell 301 also includes a field oxide regions 332, which may beformed by thermal oxidation of the substrate using the LOCOS process orby the STI process which involve the chemical vapor deposition of anoxide material as set forth above with reference to FIG. 9. The pixelcell 301 includes an oxide or other insulating film 318 deposited on thesubstrate by conventional methods, preferably a silicon dioxide grownonto the substrate 311. Doped region 352 is formed in the substrate asshown in FIG. 15 in the area that will later become the photodiode 350.As set forth above, regions 315 and 352 may be doped to the same ordifferent dopant concentration levels or a single doped region mayincorporate both regions 315 and 352. There may be other dopantimplantations applied to the wafer at this stage of processing such asn-well and p-well implants or transistor voltage adjusting implants. Forsimplicity, these other implants are not shown in the figure.

[0069] A doped polysilicon layer 320 is next deposited over the pixelcell 300 and patterned using resist and etching methods. The dopedpolysilicon layer 320 is deposited according to conventional methods.The doped polysilicon layer 320 will form the gate for the sourcefollower transistor. The gate also includes sidewall insulating spacers356 to arrive at the structure shown in FIG. 16.

[0070] An insulating layer 360 is deposited and planarized as shown inFIG. 17. The layer 360 may include materials such as BPSG, PSG, BSG orthe like. A resist layer 355 is applied to the pixel cell overinsulating layer 360 as shown in FIG. 18. A space in the resist layer355 is provided which is aligned over n-doped region 315 and a space inthe resist layer 355 is also provided over source follower transistorgate 320. The insulating layer 360 and insulating layer 318 over then-doped region 315 are then etched as shown in FIG. 19. The insulatinglayer over the source follower transistor gate 320 is also etched asshown.

[0071] A doped polysilicon layer is then deposited in the holes etchedin the insulating layer 360 to connect the n-doped region 315 and thesource follower transistor gate 320. The doped polysilicon layer is thenremoved from over the insulating layer 360 by chemical mechanicalplanarization or dry etch to provide doped polysilicon plugs 341 asshown in FIG. 20. The doped polysilicon plugs 341 may also be formed ofa composite layered structure of doped polysilicon/refractory metalsilicide or doped polysilicon/refractory metal silicide/insulator forimproved conductivity, or titanium silicide. Preferably the refractorymetal silicide is a tungsten, titanium or cobalt silicide.

[0072] The n-type dopant from in the doped polysilicon plugs 341diffuses out of the doped polysilicon and into n-doped region 315 toform contact region 325. Contact region 325 forms a good low leakagedamage free contact to n-doped region 315. It is also possible to add ann-type dopant implant into the silicon prior to polysilicon depositionto improve leakage and contact resistance.

[0073] A metal layer is then deposited over the insulating layer 360 toform a metal interconnector 370. The metal interconnector 370 serves toelectrically connect doped polysilicon plugs 341, thereby connecting thefloating diffusion region 315 and the gate 320 of the source followertransistor. The metal interconnector is deposited according toconventional methods. Preferably the metal interconnector is depositedby physical vapor deposition or sputtering or CVD. The metalinterconnector 370 may be formed of any conductive metal. Preferably themetal interconnector 370 is formed of Ti/TiN/W, Ti/Al—Cu, Ti/Al—Cu/TiN,Ti/TiN/Al—Cu/TiN, Ti/TiN/Cu, TiN/Cu or TaN/Cu.

[0074] After the processing to produce the imager shown in FIG. 21, thepixel cell 301 of the present invention is then processed according toknown methods to produce an operative imaging device. For example, apassivation layer may be applied and planarized and contact holes etchedtherein to form conductor paths to transistor gates, etc. Thepassivation layer may include materials such as BPSG, PSG, BSG or thelike. Conventional metal and insulation layers are formed over thepassivation layer and in the through holes to interconnect various partsof the circuitry in a manner similar to that used in the prior art toform the floating diffusion region to source follower gate connection.Additional insulating and passivation layers may also be applied. Theimager is fabricated to arrive at an operational apparatus thatfunctions similar to the imager depicted in FIGS. 1-4 as it should beunderstood that FIG. 21 differs from the imagers shown in FIGS. 1-4 asFIG. 21 includes a photodiode as the photocollection device as opposedto the photogate 24 illustrated in FIG. 1. Additionally, FIG. 1 shows anoptional transfer gate 28 which, as discussed above, is not needed, norillustrated, with respect to the imager depicted in FIG. 21.

[0075] The doped polysilicon plugs 341 together with the metalinterconnector 370 provide a good contact between the floating diffusionregion 315 and the source follower transistor gate 320 without usingprocessing techniques which might cause charge leakage to the substrateduring device operation. The doped polysilicon plugs 341 together withthe metal interconnector 370 also allow the source follower transistorto be placed closer to the floating diffusion region thereby allowingfor an increased photosensitive area on the pixel and short conductorbetween the floating diffusion region and gate of the source followertransistor which increases the signal to noise ratio of the imager.

[0076] A typical processor based system which includes a CMOS imagerdevice according to the present invention is illustrated generally at500 in FIG. 22. A processor based system is exemplary of a system havingdigital circuits which could include CMOS imager devices. Without beinglimiting, such a system could include a computer system, camera system,scanner, machine vision, vehicle navigation, video phone, surveillancesystem, auto focus system, star tracker system, motion detection system,image stabilization system and data compression system forhigh-definition television, all of which can utilize the presentinvention.

[0077] A processor based system, such as a computer system, for examplegenerally comprises a central processing unit (CPU) 544, for example, amicroprocessor, that communicates with an input/output (I/O) device 546over a bus 552. The CMOS imager 542 also communicates with the systemover bus 452. The computer system 500 also includes random access memory(RAM) 548, and, in the case of a computer system may include peripheraldevices such as a floppy disk drive 554 and a compact disk (CD) ROMdrive 556 which also communicate with CPU 544 over the bus 552. CMOSimager 542 is preferably constructed as an integrated circuit whichincludes the CMOS imager having a buried contact line between thefloating diffusion region and the source follower transistor, aspreviously described with respect to FIGS. 9-21. It may also bedesirable to integrate the processor 554, CMOS imager 542 and memory 548on a single IC chip.

[0078] It should again be noted that although the invention has beendescribed with specific reference to CMOS imaging circuits having aphotogate and a floating diffusion, the invention has broaderapplicability and may be used in any CMOS imaging apparatus. Forexample, the CMOS imager array can be formed on a single chip togetherwith the logic or the logic and array may be formed on separate ICchips. Additionally, while the figures describe the invention withrespect to a photodiode type of CMOS imager, any type of photocollectiondevices such as photogates, photoconductors or the like may find use inthe present invention. Similarly, the process described above are buttwo methods of many that could be used. Accordingly, the abovedescription and accompanying drawings are only illustrative of preferredembodiments which can achieve the features and advantages of the presentinvention. It is not intended that the invention be limited to theembodiments shown and described in detail herein. The invention is onlylimited by the scope of the following claims.

[0079] What is claimed as new and desired to be protected by LettersPatent of the United States is:

1. An imaging device comprising: a substrate; a photosensitive areawithin said substrate for accumulating photogenerated charge in saidarea; a floating diffusion region in said substrate for receiving chargefrom said photosensitive area; a readout circuit comprising at least anoutput transistor formed in said substrate; an insulating layer formedover said substrate; and, a doped polysilicon conductor formed in saidinsulating layer for connecting said floating diffusion region with agate of said output transistor.
 2. The imaging device according to claim1 wherein the accumulation of charge in said photosensitive area isconducted by a photoconductor.
 3. The imaging device according to claim1, wherein the accumulation of charge in said photosensitive area iscontrolled by a photogate.
 4. The imaging device according to claim 1,wherein said photosensitive area is a photodiode.
 5. The imaging deviceaccording to claim 1, further comprising a charge transfer regionbetween said photosensitive area and said floating diffusion region,said charge transfer region including a field effect transistor.
 6. Theimaging device according to claim 1, wherein said doped polysiliconconductor is a composite layered doped polysilicon/refractory metalsilicide structure.
 7. The imaging device according to claim 1, whereinsaid doped polysilicon conductor is a composite layered dopedpolysilicon/refractory metal silicide/insulator structure.
 8. Theimaging device according to claim 1, wherein said doped polysiliconconductor is a composite layered doped polysilicon/barrier metalsilicide/metal structure.
 9. The imaging device according to claim 1,including a contact between said doped polysilicon conductor and saidfloating diffusion region formed by diffusion of dopants from said dopedpolysilicon conductor into said diffusion region.
 10. The imaging deviceaccording to claim 1, wherein said substrate includes an n-type implantof arsenic or phosphorous into said substrate at a dopant concentrationof about 1.0×10¹² to about 3.0×10¹³ ions/cm².
 11. The imaging deviceaccording to claim 5, wherein the accumulation of charge in saidphotosensitive area is conducted by a photoconductor.
 12. The imagingdevice according to claim 5, wherein the accumulation of charge in saidphotosensitive area is conducted by a photogate.
 13. The imaging deviceaccording to claim 5, wherein said photosensitive area is a photodiode.14. An imaging device comprising: a substrate; a photosensitive areawithin said substrate for accumulating photogenerated charge in saidarea; a floating diffusion region in said substrate for receiving chargefrom said photosensitive area; a readout circuit comprising at least anoutput transistor formed in said substrate; an insulating layer formedover said substrate; doped polysilicon plugs formed in said insulatinglayer which contact said floating diffusion region and said outputtransistor; and an interconnector formed over said insulating layerwhich connects said doped polysilicon plugs.
 15. The imaging deviceaccording to claim 14, wherein said interconnector is metal.
 16. Theimaging device according to claim 14, wherein said interconnector isdoped polysilicon.
 17. The imaging device according to claim 14, whereinthe accumulation of charge in said photosensitive area is conducted by aphotoconductor.
 18. The imaging device according to claim 14, whereinthe accumulation of charge in said photosensitive area is controlled bya photogate.
 19. The imaging device according to claim 14, wherein saidphotosensitive area is a photodiode.
 20. The imaging device according toclaim 14, further comprising a charge transfer region between saidphotosensitive area and said floating diffusion region, said chargetransfer region including a field effect transistor.
 21. The imagingdevice according to claim 14, wherein said doped polysilicon plugs are acomposite layered doped polysilicon/barrier metal silicide/metalstructure.
 22. The imaging device according to claim 14, wherein saidsubstrate includes an n-type implant of arsenic or phosphorous into saidsubstrate at a dopant concentration of about 1.0×10¹² to about 3.0×10¹³ions/cm².
 23. The imaging device according to claim 14, including acontact between said polysilicon plug and said floating diffusion regionformed by diffusion of dopants from said doped polysilicon plug intosaid diffusion region.
 24. The imaging device according to claim 20,wherein the accumulation of charge in said photosensitive area isconducted by a photoconductor.
 25. The imaging device according to claim20, wherein the accumulation of charge in said photosensitive area isconducted by a photogate.
 26. The imaging device according to claim 20,wherein said photosensitive area is a photodiode.
 27. The imaging deviceaccording to claim 15, wherein said metal interconnector includestungsten.
 28. The imaging device according to claim 15, wherein saidmetal interconnector includes at least one of Ti, Al, W, Cu, nitridesthereof, mixtures thereof and alloys thereof.
 29. The imaging deviceaccording to claim 16, wherein said doped polysilicon conductor is acomposite layered doped polysilicon/refractory metal silicide structure.30. The imaging device according to claim 29, wherein said dopedpolysilicon conductor is a composite layered dopedpolysilicon/refractory metal silicide/insulator structure.
 31. Animaging device comprising a semiconductor integrated circuit substrate;a photosensitive device formed on said substrate for accumulatingphotogenerated charge in an underlying region of said substrate; afloating diffusion region in said substrate for receiving saidphotogenerated charge; a readout circuit comprising at least an outputtransistor formed in said substrate; an insulating layer formed oversaid substrate; and said floating diffusion region being connected tosaid output transistor by a doped polysilicon contact formed at leastpartially within said insulating layer.
 32. The imaging device accordingto claim 31, wherein said photosensitive device is a photogate.
 33. Theimaging device according to claim 31, wherein said photosensitive deviceis a photodiode.
 34. The imaging device according to claim 31, whereinsaid photosensitive device is a photoconductor.
 35. The imaging deviceaccording to claim 31, wherein a contact between said buried conductorand said floating diffusion region is formed by diffusion of dopantsfrom said doped polysilicon contact into said diffusion region.
 36. Theimaging device according to claim 31, wherein said doped polysiliconcontact is a composite layered doped polysilicon/barrier metalsilicide/metal structure.
 37. The imaging device according to claim 31,wherein said substrate includes an n-type implant of arsenic orphosphorous into said substrate at a dopant concentration of about1.0×10¹² to about 3.0×10¹³ ions/cm².
 38. The imaging device according toclaim 31, further comprising at least one charge transfer device fortransferring charge from said photosensitive area to said floatingdiffusion region in accordance with a control signal applied to acontrol terminal.
 39. The imaging device according to claim 31, whereinsaid doped polysilicon conductor is a composite layered dopedpolysilicon/refractory metal silicide structure.
 40. The imaging deviceaccording to claim 39, wherein said doped polysilicon conductor is acomposite layered doped polysilicon/refractory metal silicide/insulatorstructure.
 41. The imaging device according to claim 31, wherein saidoutput transistor is formed adjacent to said floating diffusion regionon said substrate.
 42. The imaging device according to claim 31, furthercomprising a reset transistor for resetting said floating diffusionregion to a predetermined voltage.
 43. The imaging device according toclaim 31, wherein said floating diffusion region is an n-doped region ina p-well.
 44. The imaging device according to claim 32, wherein saidphotogate is formed of doped polysilicon.
 45. The imaging deviceaccording to claim 33, further comprising a lightly doped n regionbeneath said photodiode.
 46. An imaging device comprising asemiconductor integrated circuit substrate; a photosensitive deviceformed on said substrate for accumulating photogenerated charge in anunderlying region of said substrate; a floating diffusion region in saidsubstrate for receiving said photogenerated charge; a readout circuitcomprising at least an output transistor formed in said substrate; aninsulating layer formed over said substrate; and doped polysilicon plugsformed in said insulating layer which contact said floating diffusionregion and said output transistor; and an interconnector formed oversaid insulating layer which connects said doped polysilicon plugs. 47.The imaging device according to claim 46, wherein said interconnector isa metal.
 48. The imaging device according to claim 46, wherein saidinterconnector is doped polysilicon.
 49. The imaging device according toclaim 46, wherein said photosensitive device is a photogate.
 50. Theimaging device according to claim 46, wherein said photosensitive deviceis a photodiode.
 51. The imaging device according to claim 46, whereinsaid photosensitive device is a photoconductor.
 52. The imaging deviceaccording to claim 46, including a contact between said dopedpolysilicon plug and said floating diffusion region formed by diffusionof dopants from said doped polysilicon plug into said diffusion region.53. The imaging device according to claim 46, further comprising atleast one charge transfer device for transferring charge from saidphotosensitive area to said floating diffusion region in accordance witha control signal applied to a control terminal.
 54. The imaging deviceaccording to claim 46, wherein said doped polysilicon plugs are acomposite layered doped polysilicon/barrier metal silicide/metalstructure.
 55. The imaging device according to claim 46, wherein saidsubstrate includes an n-type implant of arsenic or phosphorous into saidsubstrate at a dopant concentration of about 1.0×10¹² to about 3.0×10¹³ions/cm².
 56. The imaging device according to claim 46, wherein saidoutput transistor is formed adjacent to said floating diffusion regionon said substrate.
 57. The imaging device according to claim 46, furthercomprising a reset transistor for resetting said floating diffusionregion to a predetermined voltage.
 58. The imaging device according toclaim 46, wherein said floating diffusion region is an n-doped region ina p-well.
 59. The imaging device according to claim 49, wherein saidphotogate is formed of doped polysilicon.
 60. The imaging deviceaccording to claim 50, further comprising a lightly doped n regionbeneath said photodiode.
 61. The imaging device according to claim 47,wherein said metal interconnector includes tungsten.
 62. The imagingdevice according to claim 47, wherein said metal interconnector includesat least one of Ti, Al, W, Cu, nitrides thereof, mixtures thereof andalloys thereof.
 63. The imaging device according to claim 48, whereinsaid doped polysilicon conductor is a composite layered dopedpolysilicon/refractory metal silicide structure.
 64. The imaging deviceaccording to claim 63, wherein said doped polysilicon conductor is acomposite layered doped polysilicon/refractory metal silicide/insulatorstructure.
 65. A method for generating output signals corresponding toan image focused on a sensor array having rows and columns of pixelsensors, the method comprising the steps of: sequentially activatingeach row of sensors of said array for a period of time; detecting afirst voltage at a node of an activated sensor, which corresponds tocollected charges produced by a detected image; resetting the voltage ofsaid node to a first predetermined voltage by a reset transistor;transferring image generated electrical charges collected by saidactivated sensor to said node, the voltage at the node changing from afirst reset voltage to a second voltage corresponding to the respectiveamount of transferred electrical charges; detecting the second voltageat the node of said activated sensor; and generating an output signal bytransferring charge from said node of said activated sensor to an outputtransistor via a doped polysilicon contact formed on an insulatinglayer.
 66. The method for generating an output signal according to claim65, wherein said activated sensor is a photogate.
 67. The method forgenerating an output signal according to claim 65, wherein saidactivated sensor is a photodiode.
 68. The method for generating anoutput signal according to claim 65, wherein said activated sensor is aphotoconductor.
 69. The method for generating an output signal accordingto claim 65, wherein said transferring of electrical charges collectedby said activated sensor to said diffusion well is performed by a fieldeffect transistor.
 70. The method for generating an output signalaccording to claim 65, wherein said diffusion node is a floatingdiffusion node.
 71. The method for generating an output signal accordingto claim 65, wherein a contact between said buried conductor and saidnode is formed by diffusion of dopants from said doped polysiliconcontact into said diffusion region.
 72. The method for generating anoutput signal according to claim 65, wherein said doped polysiliconconyact is a composite layered doped polysilicon/barrier metalsilicide/metal structure.
 73. The method for generating an output signalaccording to claim 65, wherein said substrate includes an n-type implantof arsenic or phosphorous into said substrate at a dopant concentrationof about 1.0×10¹² to about 3.0×10³ ions/cm².
 74. The method forgenerating an output signal according to claim 65, wherein said dopedpolysilicon conductor is a composite layered dopedpolysilicon/refractory metal silicide structure.
 75. The method forgenerating an output signal according to claim 74, wherein said dopedpolysilicon conductor is a composite layered dopedpolysilicon/refractory metal silicide/insulator structure.
 76. Animaging system for generating output signals based on an image focusedon the imaging system, the imaging system comprising: a plurality ofpixel cells arranged into an array of rows and columns, each pixel cellbeing operable to generate a voltage at a diffusion node correspondingto detected light intensity by the cell; a row decoder having aplurality of control lines connected to the cell array, each controlline being connected to the cells in a respective row, wherein the rowdecoder is operable to activate the cells in a row; and a plurality ofoutput circuits each including a respective output transistor, eachoutput circuit being connected to a respective cell of said array, eachcircuit being operable to store voltage signals received from arespective cell and to provide a cell output signal; and a plurality ofdoped polysilicon contacts for respectively interconnecting a diffusionnode of a pixel cell with a gate of a source follower transistor. 77.The imaging system according to claim 76, wherein said output transistoris a source follower transistor and the diffusion node is connected tosaid source follower transistor by a buried contact connection formedover an insulating layer formed over the substrate of said pixel cell.78. The imaging system according to claim 76, wherein said active pixelcells include a photogate.
 79. The imaging system according to claim 76,wherein said active pixel cells include a photodiode.
 80. The imagingsystem according to claim 76, wherein said active pixel cells include aphotoconductor.
 81. The imaging system according to claim 77, whereinsaid source follower transistor is formed adjacent to said diffusionnode.
 82. The imaging system according to claim 76, further comprisingat least one charge transfer device for transferring charge from aphotosensitive area to a floating diffusion region in said pixel cell inaccordance with a control signal applied to a control terminal.
 83. Theimaging system according to claim 76, wherein said doped polysiliconcontacts are a composite layered doped polysilicon/barrier metalsilicide/metal structure.
 84. The imaging system according to claim 76,wherein said substrate includes an n-type implant of arsenic orphosphorous into said substrate at a dopant concentration of about1.0×10¹² to about 3.0×10¹³ ions/cm².
 85. The imaging system according toclaim 76, wherein said doped polysilicon conductor is a compositelayered doped polysilicon/refractory metal silicide structure.
 86. Theimaging system according to claim 76, including a contact between saiddoped polysilicon contact and said floating diffusion region formed bydiffusion of dopants from said doped polysilicon contact into saiddiffusion region.
 87. The imaging system according to claim 82, whereinthe accumulation of charge in said photosensitive area is conducted by aphotoconductor.
 88. The imaging system according to claim 82, whereinthe accumulation of charge in said photosensitive area is conducted by aphotogate.
 89. The imaging system according to claim 82, wherein saidphotosensitive area is a photodiode.
 90. A processing system comprising:(i) a processor; and (ii) a CMOS imaging device coupled to saidprocessor and including: a substrate; a photosensitive area within saidsubstrate for accumulating photogenerated charge in said area; afloating diffusion region in said substrate for receiving charge fromsaid photosensitive area; a readout circuit comprising at least anoutput transistor formed in said substrate; an insulating layer formedover said substrate; and a doped polysilicon conductor formed at leastpartially within said insulating layer for interconnecting said floatingdiffusion region with said output transistor.
 91. The system accordingto claim 90, further comprising at least one charge transfer device fortransferring charge from said photosensitive area to said floatingdiffusion region in accordance with a control signal applied to acontrol terminal.
 92. The system according to claim 90, wherein theaccumulation of charge in said photosensitive area is conducted by aphotogate.
 93. The system according to claim 90, wherein saidphotosensitive area is a photodiode.
 94. The system according to claim90, wherein said photosensitive area is a photoconductor.
 95. The systemaccording to claim 90, including a contact between said buried conductorand said floating diffusion region formed by diffusion of dopants fromsaid doped polysilicon conductor into said diffusion region.
 96. Thesystem according to claim 90, wherein said doped polysilicon conductoris a composite layered doped polysilicon/barrier metal silicide/metalstructure.
 97. The system according to claim 90, wherein said substrateincludes an n-type implant of arsenic or phosphorous into said substrateat a dopant concentration of about 1.0×10¹² to about 3.0×10¹³ ions/cm².98. The system according to claim 90, wherein said doped polysiliconconductor is a composite layered doped polysilicon/refractory metalsilicide structure.
 99. The system according to claim 98, wherein saiddoped polysilicon conductor is a composite layered dopedpolysilicon/refractory metal silicide/insulator structure.
 100. Thesystem according to claim 91, wherein the accumulation of charge in saidphotosensitive area is controlled by a photoconductor.
 101. The systemaccording to claim 91, wherein the accumulation of charge in saidphotosensitive area is controlled by a photogate.
 102. The systemaccording to claim 91, wherein said photosensitive area is a photodiode.103. A processing system comprising: (i) a processor; and (ii) a CMOSimaging device coupled to said processor and including: a substrate; aphotosensitive area within said substrate for accumulatingphotogenerated charge in said area; a floating diffusion region in saidsubstrate for receiving charge from said photosensitive area; a readoutcircuit comprising at least an output transistor formed in saidsubstrate; an insulating layer formed over said substrate; dopedpolysilicon plugs formed in said insulating layer which contact saidfloating diffusion region and said output transistor; and aninterconnector formed over said insulating layer which connects saiddoped polysilicon plugs.
 104. The system according to claim 103, whereinsaid interconnector is a metal.
 105. The system according to claim 103,wherein said interconnector is doped polysilicon.
 106. The systemaccording to claim 103, further comprising at least one charge transferdevice for transferring charge from said photosensitive area to saidfloating diffusion region in accordance with a control signal applied toa control terminal.
 107. The system according to claim 103, wherein theaccumulation of charge in said photosensitive area is conducted by aphotogate.
 108. The system according to claim 103, wherein saidphotosensitive area is a photodiode.
 109. The system according to claim103, wherein said photosensitive are is a photoconductor.
 110. Thesystem according to claim 103, including a contact between said dopedpolysilicon plug and said floating diffusion region formed by diffusionof dopants from said doped polysilicon plug into said diffusion region.111. The system according to claim 103, wherein said interconnector is acomposite layered doped polysilicon/barrier metal silicide/metalstructure.
 112. The system according to claim 103, wherein saidsubstrate includes an n-type implant of arsenic or phosphorous into saidsubstrate at a dopant concentration of about 1.0×10¹² to about 3.0×10¹³ions/cm².
 113. The system according to claim 106, wherein theaccumulation of charge in said photosensitive area is controlled by aphotoconductor.
 114. The system according to claim 106, wherein theaccumulation of charge in said photosensitive area is controlled by aphotogate.
 115. The system according to claim 106, wherein saidphotosensitive area is a photodiode.
 116. The system according to claim105, wherein said doped polysilicon conductor is a composite layereddoped polysilicon/refractory metal silicide structure.
 117. The systemaccording to claim 116, wherein said doped polysilicon conductor is acomposite layered doped polysilicon/refractory metal silicide/insulatorstructure.
 118. The system according to claim 104, wherein said metalinterconnector includes tungsten.
 119. The system according to claim104, wherein said metal interconnector includes at least one of Ti, Al,W, Cu, nitrides thereof, mixtures thereof and alloys thereof.
 120. Amethod of forming a contact line between a diffusion node and an outputtransistor in a CMOS imager, comprising the steps of: providing asubstrate having a first conductivity; forming a diffusion region havinga second conductivity in said substrate which functions as saiddiffusion node; forming an insulating layer on said substrate; formingan output transistor on said substrate; selectively removing at least aportion of said insulating layer over said diffusion region; selectivelyremoving at least a portion of said insulating layer over the gate ofsaid output transistor; and forming a continuously conductive layer ofdoped polysilicon directly over at least a portion of said insulatinglayer to connect said diffusion contact and said output transistor gate.121. The method according to claim 120, wherein said insulating layer issilicon dioxide.
 122. The method according to claim 120, wherein acontact between said doped polysilicon conductor and said floatingdiffusion region is formed by diffusion of dopants from said dopedpolysilicon conductor into said diffusion region.
 123. The methodaccording to claim 120, further comprising forming a composite layereddoped polysilicon/barrier metal silicide/metal structure to connect saiddiffusion contact with said output transistor gate.
 124. The methodaccording to claim 120, wherein said substrate of a first conductivityincludes an n-type implant of arsenic or phosphorous into said substrateat a dopant concentration of about 1.0×10¹² to about 3.0×10¹³ ions/cm².125. The method according to claim 120, further comprising forming arefractory metal silicide layer around the periphery of said polysiliconconductive layer.
 126. The method according to claim 125, furthercomprising an insulating layer around the periphery of said refractorymetal silicide layer.
 127. The method according to claim 120, whereinsaid first conductivity type is p-type and said second conductivity typeis n-type.
 128. The method according to claim 120, wherein said outputtransistor is a source follower transistor formed adjacent to saiddiffusion region.
 129. The method according to claim 120, wherein saidinsulating layer is removed by etching.
 130. A method of forming aburied contact line between a diffusion node and an output transistor ina CMOS imager, comprising the steps of: providing a substrate having afirst conductivity; forming a diffusion region having a secondconductivity in said substrate which functions as said diffusion node;forming an insulating layer on said substrate; forming an outputtransistor on said substrate; selectively removing at least a portion ofsaid insulating layer to form a first trench over said diffusion region;selectively removing at least a portion of said insulating layer toforma second trench over the gate of said output transistor; formingfirst and second conductive doped polysilicon plugs in said first andsecond trenches respectively; and forming a metal interconnector oversaid insulating layer to connect said diffusion contact and said outputtransistor gate by connecting said first and second doped polysiliconplugs.
 131. The method according to claim 130, wherein said insulatinglayer is silicon dioxide.
 132. The method according to claim 130,wherein a contact between said first doped polysilicon plug and saidfloating diffusion region is formed by diffusion of dopants from saidfirst doped polysilicon plug into said diffusion region.
 133. The methodaccording to claim 130, wherein said substrate of a first conductivityincludes an n-type implant of arsenic or phosphorous into said substrateat a dopant concentration of about 1.0×10¹² to about 3.0×10¹³ ions/cm².134. The method according to claim 130, wherein said first conductivitytype is p-type and said second conductivity type is n-type.
 135. Themethod according to claim 130, wherein said output transistor is asource follower transistor formed adjacent to said diffusion region.136. The method according to claim 130, wherein said insulating layer isremoved by etching.
 137. The method according to claim 130, wherein saidmetal interconnector is formed of at least a tungsten metal.
 138. Themethod according to claim 130, wherein said metal interconnectorincludes at least one of Ti, Al, W, Cu, nitrides thereof, mixturesthereof and alloys thereof.
 139. The method according to claim 137,wherein said metal is deposited by sputtering.
 140. The method accordingto claim 138, wherein said metal is deposited by sputtering.
 141. Amethod of forming a contact line between a floating diffusion node and asource follower transistor in a CMOS imager, comprising the steps of:providing a semiconductor substrate doped to a first conductivity;forming a floating diffusion region of a second conductivity in saidsubstrate; forming an insulating layer of silicon dioxide over at leasta portion of said substrate; forming a source follower transistoradjacent to said floating diffusion region; selectively removing atleast a portion of said insulating layer over the gate of said outputtransistor; selectively etching at least a portion of said insulatinglayer to over said diffusion region and said source follower transistorgate; forming a doped polysilicon layer on at least a portion of saidinsulating layer to connect said floating diffusion contact and saidsource follower transistor gate.
 142. The method according to claim 141,wherein a contact between said doped polysilicon layer and said floatingdiffusion region is formed by diffusion of dopants from said dopedpolysilicon conductor into said floating diffusion region.
 143. Themethod according to claim 141, wherein said substrate includes an n-typeimplant of arsenic or phosphorous into said substrate at a dopantconcentration of about 1.0×10¹² to about 3.0×10¹³ ions/cm².
 144. Amethod of forming a buried contact line between a diffusion node and anoutput transistor in a CMOS imager, comprising the steps of: providing asubstrate having a first conductivity; forming a diffusion region havinga second conductivity in said substrate which functions as saiddiffusion node; forming an insulating layer of silicon dioxide over atleast a portion of said substrate, wherein said insulating layer isformed over at least said floating diffusion region; forming an outputtransistor area over said substrate; selectively removing at least aportion of said insulating layer to form a diffusion contact area oversaid diffusion region; and forming a continuously conductive layer ofdoped polysilicon directly in said insulating layer to connect saiddiffusion contact and said output transistor.
 145. The method accordingto claim 144, wherein said insulating layer is silicon dioxide.
 146. Themethod according to claim 144, further comprising forming a refractorymetal silicide layer over a periphery of said polysilicon conductivelayer.
 147. The method according to claim 144, wherein said firstconductivity type is p-type and said second conductivity type is n-type.148. The method according to claim 144, wherein said output transistoris a source follower transistor formed adjacent to said diffusionregion.
 149. The method according to claim 144, wherein said insulatinglayer is removed by etching.